FTXL 3190 Free Topology Transceiver Solution FAQWhat applications need the FTXL solution? The FTXL solution is suitable for all high-performance system-, area-, and zone-level controllers. These devices may be used in various markets such as building controls, lighting controls, and industrial controls, as well as in safety applications and high-end window blind controllers. How does the FTXL solution compare to Smart Transceiver- or ShortStack-based solutions?
How does the FTXL solution compare to the MIP? The MIP requires far more development to create a complete LonTalk enabled device. The MIP requires manual construction of all initialization data and device interface (XIF) files, and implementation of LonTalk protocol layers above layer 4. It’s also restricted by the address table and transaction limitations that exist in single-chip Smart Transceiver and Neuron Chip devices. The MIP can target any host microprocessor, while the FTXL solution is limited to running on the Nios II embedded processor configured on an Altera Cyclone II/III family FPGA. The FTXL solution is limited to the TP/FT-10 channel, while the MIP can target any LonWorks channel. The MIP requires a runtime royalty, while the FTXL solution is royalty-free. How do I start developing with the FTXL solution? The free FTXL Developer's Kit gives you everything you need to get started. What components are needed for an application based on the FTXL solution? A typical FTXL device includes the following components:
Can I use the FTXL 3190 Transceiver with a processor platform other than the Altera FPGA? The FTXL solution is available only for an Altera Cyclone II/III FPGA host. When will the FTXL solution be available? The FTXL Developer's Kit is available as a free download now. The FTXL 3190 Transceiver will be available in February 2008. How does the FTXL solution compare with a microprocessor not implemented with an FPGA? The FTXL solution executes on the Nios II 32-bit embedded RISC processor, which is a soft-core processor implemented on an Altera Cyclone II or III FPGA. Using the Altera FPGA design tools (Quartus II and SOPC Builder), a hardware designer selects options that affect the performance of the final solution. The processor input clock can be as high as 195 MHz, with DMIPs performance as high as 165 DMIPs. Benchmark data is available from Altera (Nios II benchmark results).Does the FTXL solution work with all twisted pair and power line channels? The FTXL solution works only with a TP/FT-10 Twisted Pair Free Topology channel. It does not work with any other channel types, including power line (PL-20) channel. The FTXL chip is a special transceiver that implements layers 1 and 2 of the LonTalk protocol. There is no equivalent version with a PL-20 transceiver. Power line device developers can use the ShortStack solution to create LonWorks devices with up to 254 network variables.
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